Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive and require less time to implement than semi-custom and custom integrated circuits.
One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBs, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable elements may be customized by loading configuration data into internal configuration memory cells that, by determining the state of various programming points, define how the CLBs, interconnections, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA from an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One prior art FPGA, for example one device of the Xilinx XC4000.TM. family of FPGAs commercially available from Xilinx, Inc., includes one configuration memory cell to control each programming point. As shown in FIG. 1, a conventional memory cell 101, in one embodiment a latch 103, and an access transistor 105 compromise a five-transistor memory cell that forms the basic control unit for all logic functions on the FPGA. In the embodiment of FIG. 1, signals on a word line WORD and a bit line BIT conventionally control the program state of memory cell 101, which in turn controls the state of a conventional pass transistor 107. U.S. Pat. No. 4,821,233, which issued on Apr. 11, 1989, and U.S. Pat. No. 4,750,155, which issued on Jun. 7, 1988 (both patents incorporated herein by reference), discuss some appropriate configurations for the memory cell of FIG. 1.
FPGAs can be reconfigured any number of times by simply reprogramming the configuration memory cells. Some FPGA applications take advantage of this feature by providing an external memory that includes a number N sets of configuration memory, each of which may be programmed to store a different set of configuration data. The FPGA may then be quickly and easily reprogrammed to function in one of N configurations. Moreover, complex logic functions can be implemented by dynamically reconfiguring the FPGA to sequentially perform more than one logic function on a given set of input signals. Unfortunately, each reconfiguration may require a number of steps that are collectively time consuming, especially in applications that require frequent reconfiguration.
A partial solution to this speed problem involves integrating the reconfiguration memory and associated read/write control circuitry with the FPGA onto a single chip, or die. In one such FPGA, as depicted in FIG. 2, each memory cell 101 of FIG. 1 is replaced with a random access memory (RAM) bit set 200. Bit set 200 includes eight memory cells MC0-MC7. Each memory cell MC is connected via an associated access transistor and a common bit line 203 to a clocked latch 204. Each of memory cells MC0-MC7 can contain different configuration data. That data can then be selectively transferred into latch 204 to control conventional programming points, such as multiplexer control lines, look-up table bits, or, as in the example, a pass transistor 107. For a more detailed description of the circuit of FIG. 2, see U.S. Pat. No. 5,646,545, entitled "Time Multiplexed Programmable Logic Device," issued Jul. 8, 1997, which is incorporated herein by reference.
Integrating the configuration memory and read/write control circuitry with the FPGA solves many problems associated with dynamic reconfiguration; there is still substantial room for improvement, however. For example, the reconfiguration memory, read/write control circuitry, and additional word lines occupy a large percentage of available chip area. Increasing chip area is expensive and slows the logic function of the FPGA.